1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a MOS transistor having a salicide structure by using titanium.
2. Description of the Related Art
As a semiconductor device is more and more reduced in size, it is required for a source/drain diffusion layer, which constitutes a part of a source/drain region of a MOS transistor, to have shallower junction depth. In addition, it is further required for a source/drain region to have a lower resistance, as well as to have a source/drain diffusion layer having a shallow junction depth.
One of methods for satisfying such requirements is a method comprising the steps of forming a diffusion layer having shallow junction depth, and forming titan silicide (TiSi.sub.2) on a surface of the diffusion layer. Such a method has been proposed, for instance, in Japanese Unexamined Patent Publication No. 2-1120.
With reference to FIGS. 1A to 1D which are cross-sectional views showing fabrication steps of a semiconductor, hereinbelow is explained the method disclosed in Japanese Unexamined Patent Publication No. 2-1120.
With reference to FIG. 1A, field oxide films 402 are formed on a silicon substrate 401 in device isolation regions. Then, a gate oxide film 403 is formed in a region in which a device is to be formed, and subsequently a polysilicon gate electrode 404 is formed on the gate oxide film 403. A silicon dioxide film is deposited all over a resultant, and then the silicon dioxide film is etched-back to form a sidewall spacer 405 along a sidewall of the polysilicon gate electrode 404. The sidewall spacer 405 is composed of the silicon dioxide film.
Then, highly concentrated impurities are ion-implanted into a region in which a source/drain region is to be formed, to thereby form a source/drain diffusion layer 406 having junction depth of 0.1 .mu.m. Subsequently, a titanium film 428 having a thickness of 100 nm and an amorphous silicon film 429 having a thickness of 200 nm are successively deposited on a resultant. FIG. 1A shows the state after the films 428 and 429 have been deposited.
Then, the amorphous silicon film 429 is patterned by conventional photolithography so that a portion of the amorphous silicon film 429 disposed on the polysilicon gate electrode 404 is removed. By the patterning, portions 429a of the amorphous silicon film 429 is left not removed. Ends of the portions 429a of the amorphous silicon film are disposed above the sidewall spacer 405, as illustrated in FIG. 1B.
Subsequently, rapid thermal annealing (RTA) is carried out at 600 degrees centigrade to cause silicidation process, which makes the polysilicon gate electrode 404 react with the titanium film 428 to thereby form a TiSi.sub.2 film 430A covering an upper surface of the polysilicon gate electrode 404. The reaction of the amorphous silicon film 429 with the titanium film 428 also forms a TiSi.sub.2 film 430B covering the source/ drain diffusion layer 406 and field oxide films 402. Portion 428a of the titanium film 428 remain unreacted on the sidewall spacer 405, sandwiched between the TiSi.sub.2 films 430A and 430B, as illustrated in FIG. 1C.
Then, only the unreacted titanium films 428a are selectively removed by etching to thereby form a semiconductor device, as illustrated in FIG. 1D.
According to the No. 2-1120, the titanium film 428 does not react with the source/drain diffusion layer 406 in the above mentioned silicidation process due to the amorphous silicon film 429a present on the source/drain diffusion layer 406. Thus, the source/drain diffusion layer 406 is able to have shallow junction depth, and the source/drain region is able to have a lower resistance due to the TiSi.sub.2 film 430B disposed in direct contact with a surface of the source/drain diffusion layer 406.
Another methods of fabricating a MOS transistor including a source/drain diffusion layer having shallower junction depth, which layer constitutes a part of a source/drain region, and a source/drain region having a lower resistance, have been suggested in Japanese Unexamined Patent Publication No. 2-222153 and Mark Rodder et al., "Raised Source/Drain MOSFET with Dual Sidewall Spacers", IEEE Electron Device Letters, Vol. 12, No. 3, pp 89-91, March 1991. These methods comprise the steps of making a thin single crystal silicon layer epitaxial-grow on a silicon substrate in a region in which a source/drain diffusion layer is to be formed, forming a source/drain diffusion layer having equivalently deep junction depth, and silicidizing a surface of the source/drain diffusion layer.
With reference to FIGS. 2A to 2E which are cross-sectional views showing fabrication steps of a semiconductor device, hereinbelow is explained in detail the method of fabricating a semiconductor device having been proposed in Japanese Unexamined Patent Publication No. 2-222153.
First, with reference to FIG. 2A, field oxide films 502 are formed in device isolation regions on a p-type silicon substrate 501. Then, a gate oxide film 503 having a thickness ranging from 5 to 90 nanometers is formed in a region in which a device is to be formed, and subsequently a polysilicon gate electrode 504 is deposited on the gate oxide film 503. The polysilicon gate electrode 504 is covered at an upper surface thereof with a silicon dioxide film 513 having a thickness in the range from 50 to 100 nanometers.
Then, ion-implanting is carried out using the field oxide films 502 and the polysilicon gate electrode 504 as a mask to thereby form a N- diffusion layer 526 including impurities at the concentration ranging from 5.times.10.sup.17 to 1.times.10.sup.20 cm.sup.-3. Then, a silicon dioxide film having a thickness ranging from 20 to 90 nanometers is deposited all over a resultant. The gate oxide film 503 and the silicon dioxide film are etched back to thereby form a first sidewall spacer 505 along a sidewall of the polysilicon gate electrode 504. The etching also forms a natural oxidation film 516 over a surface of the N- diffusion layer 526. FIG. 2A illustrates this stage.
Then, as illustrated in FIG. 2B, the natural oxidation film 516 is removed. Then, as illustrated in FIG. 2C, a single crystal silicon layer 536 having a thickness ranging from 100 to 200 nanometers is made to epitaxially grow on a surface of the N- diffusion layer 526. The single crystal silicon layer 536 has facets.
Then, a silicon dioxide film having a thickness in the range from 100 to 200 nanometers is deposited over a resultant. The thus deposited silicon dioxide film together with the silicon dioxide film 513 are etched back to thereby form a second sidewall spacer 515 covering the sides of the first sidewall spacer 505, and further thereby expose an upper surface of the polysilicon gate electrode. Subsequently, an N+ diffusion layer 546 is formed, for instance, by ion-implanting using the field oxide films 502 and the sidewall spacers 505 and 515 as a mask.
As illustrated in FIG. 2D, the thus formed N+ diffusion layer 546 passes through the N- diffusion layer 526. Herein, the reason why the second sidewall spacer 515 is formed is to avoid the junction depth of the N+ diffusion layer 546 just beneath the facets of the single crystal silicon layer 536 from being locally deep on ion-implanting for the formation of the N+ diffusion layer 546.
Then, a titanium film is deposited all over a resultant. Then, rapid thermal annealing (RTA) is carried out in nitrogen atmosphere to thereby selectively deposit TiSi.sub.2 films 554 and 556 on surfaces of the polysilicon gate electrode 504 and the N+ diffusion layer 546, respectively.
Subsequently, unreacted portions of the titanium film and the titanium nitride film are selectively removed to thereby complete an N channel MOS transistor having salicide structure. FIG. 2E illustrates the thus fabricated MOS transistor. A source/drain region 506 of this transistor is composed of the N- diffusion layer 526, the N+ diffusion layer 546 and the TiSi.sub.2 film 556.
Though the N- diffusion layer 526 has the equivalently deep junction depth, the effective junction depth is shallower when measured on the basis of a surface of the original p-type silicon substrate 501. Thus, the method proposed in No. 2-222153 makes it possible to make junction depth of a source/drain diffusion layer shallower and lower the resistivity of a source/drain region due to the above mentioned effectively shallower junction depth and the presence of the TiSi.sub.2 film 556.
In the firstly mentioned conventional method, the source/drain diffusion layer 406 has shallow junction depth, and thus it is necessary to arrange a thickness of the titanium film 428 to be thin accordingly. Thus, this method has a difficulty of forming a diffusion layer having shallow junction depth. In addition, it is also difficult to lower the resistivity of a source/drain region due to a thin thickness of the TiSi.sub.2 film which is caused due to a thin thickness of the titanium film. In further addition, in order to carry out photolithography so that the amorphous silicon film 429a has to be left unremoved, the sidewall spacer 405 is required to have a width greater than an alignment margin to be used in the photolithography steps. In order to avoid offset of the source/drain diffusion layer 406 and the polysilicon gate electrode 404 under such requirement, it is not allowed to arrange the junction depth of the source/drain diffusion layer 406 to be so shallow. Furthermore, the TiSi.sub.2 film 430B, which is in direct contact with a surface of the source/drain diffusion layer 406, is not formed in self-alignment to the source/drain diffusion layer 406, and hence it is necessary to carry out patterning of the TiSi.sub.2 film 430B again. In conclusion, it is quite difficult to apply this method to the fabrication of a remarkably small-sized semiconductor device.
On the other hand, the secondly mentioned conventional method needs the removal of the natural oxidation film 516 and the selective epitaxial growth of the single crystal silicon layer 536 by CVD, and thus the decrease in fabrication yield is unavoidable. In addition, this method needs the formation of the second sidewall spacer 515 together with the N- diffusion layer 526 in order to overcome a problem caused due to the facets of the single crystal silicon layer 536, and accordingly a margin or gap between the N+ diffusion layer 546 and the polysilicon gate electrode 504 has to be present. Thus, it is also difficult to apply this method to the fabrication of a remarkably small-sized semiconductor device.